Multi-channel timing analyzers are normally designed with the capability of generating pattern-match triggers encompassing all or a selected portion of the inputs to the analyzer. When the inputs match a particular pattern defined by the user, an output signal goes true which then triggers the start or stop of a data acquisition cycle.
Pattern trigger duration circuits are used to qualify the presence of a particular pattern by requiring it to be present for a defined period of time before it is recognized. Some circuits accomplish this by requiring a pattern to exist for a pre-set number of samples; others use analog timing circuitry for the duration qualification. The analog approach has an advantage in that an output trigger can be generated and used to trigger oscilloscopes, whereas circuits which synchronize the trigger to an internal sample clock cause jitter on the oscilloscope, making this feature much less useful.
This disclosure describes a technique for generating analog pattern duration qualification where the condition required can be pattern duration longer than a pre-set value, shorter than a pre-set value, or simply a transition into or away from the specified pattern. In addition, the capability of combining triggering on a particular group of inputs entering (or leaving) one state, when a second group of inputs have been in another state for a pre-settable time duration, is also described. The outputs of one or more trigger qualification circuits are combined to achieve these results. Each trigger qualification circuit includes a transition detector and variable time duration comparator, from whose outputs various logical combinations are derived that represent the desired trigger condition.